PUBLICATIONS

  • Publications of the HMTT

2023

  • ○ Xu Zhang, Tianyue Lu, Yisong Chang, Ke Zhang and Mingyu Chen,"Morpheus: An Adaptive DRAM Cache with Online Granularity Adjustment for Disaggregated Memory",2023 IEEE International Conference on Computer Design (ICCD),November 6 – 8, 2023, Washington DC, US

  • ○ Haifeng Li, Ke Liu, Ting Liang, Zuojun Li, Tianyue Lu, Hui Yuan, Yinben Xia, Yungang Bao, Mingyu Chen, Yizhou Shan，“MARB: Bridge the Semantic Gap between Operating System and Application Memory Access Behavior",Design, Automation and Test in Europe Conference (DATE-2023) , 17-19 April, 2023，Antwerp,BE

  • ○  Haifeng Li, Ke Liu, Ting Liang, Zuojun Li, Tianyue Lu, Hui Yuan, Yinben Xia, Yungang Bao, Mingyu Chen, Yizhou ,"HoPP: Hardware-Software Co-Designed Page Prefetching for Disaggregated Memory", The 29th IEEE International Symposium on High-Performance Computer Architecture (HPCA-29)，Feb. 25-Mar. 01 2023,Montreal, QC, Canada

2021

  • ○ Haiyang Pan, Yuhang Liu, Tianyue Lu, Mingyu Chen, “LSP: Collective Cross-Page Prefetching for NVM”,Design, Automation and Test in Europe Conference(DATE-2021)，01-05,Feburary 2021

2018

  • Jiutian Zhang, Yuhang Liu, Haifeng Li, Xiaojing Zhu, Mingyu Chen,”PTAT: An Efficient and Precise Tool for Tracing and Profiling Detailed TLB Misses”, ACM Transactions on Embedded Computing Systems (TECS), Volumn 17, Issue 3, Article 62, May 2018

2017

  • Tianyue Lu, Yuhang Liu, Mingyu Chen, “Fine-Grained Data Committing for Persistent Memory”, in The 15th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA), Guangzhou, China, December 12-15, 2017
  • Tianyue Lu, Yuhang Liu, Haiyang Pan and Mingyu Chen,”TDV cache: Organizing Off-Chip DRAM Cache of NVMM from a Fusion Perspective”,The 35th IEEE International Conference on Computer Design (ICCD),November 5 – 8, 2017, Boston Area,Massachusetts, USA
  • Wei wei，Dejun Jiang,Jin Xiong,Mingyu Chen, “HAP: Hybrid-Memory-Aware Partition in Shared Last-Level Cache”, ACM Transactions onArchitecture and Code Optimization (TACO), Volume 14 Issue 3, September 2017 , Article No. 24

2016

  • Zehan Cui, Tianyue Lu,Sally A. McKee,Mingyu Chen, Haiyang Pan,Yuan Ruan,”Twin-Load: Bridging the Gap between Conventional Direct-Attached and Buffer-on-Board Memory Systems”,The International Sysmposium on Memory Systems(MemSYS), Oct. 2016,Washington DC, USA.
  • Ke Zhang, Lei Yu, Hongxia Zhang, Ran Zhao, Yisong Chang, Mingyu Chen, Lixin Zhang,”Co-DIMM: Inter-socket Data Sharing with Common DIMM Channel”,The International Sysmposium on Memory Systems(MemSYS), Oct. 2016,Washington DC, USA.

2015

  • Zhipeng Wei, Zehan Cui, Mingyu Chen,”Cracking Intel Sandy Bridge’s Cache Hash Function”, arXiv:1508.03767
  • Wei Wei, Dejun Jiang, Sally A. McKee, Jin Xiong and Mingyu Chen, “Exploiting Program Semantics to Place Data in Hybrid Memory”, The 24th International Conference on Parallel Architectures and Compilation Techniques(PACT) October 18-21, San Francisco, CA, USA

2014

  • Zehan Cui, Sally A. McKee, Zhongbin Zha, Yungang Bao, Mingyu Chen. DTail: A Flexible Approach to DRAM Refresh Management, ACM International Conference on Supercomputing (ICS), 2014. [pdf]
  • Zehan Cui, Licheng Chen, Yungang Bao, Mingyu Chen. A Swap-based Cache Set Index Scheme to Leverage both Superpage and Page Coloring Optimizations, to appear in the Design Automation Conference (DAC), 2014.[pdf]
  • Yongbing Huang, Licheng Chen, Zehan Cui, Yuan Ruan, Yungang Bao, Mingyu Chen, and Ninghui Sun. HMTT: A hybrid hardware/software tracing system for bridging the DRAM access trace's semantic gap. ACM Trans. Archit. Code Optim. (ACM TACO) 11, 1, Article 7 (February 2014), 25 pages. DOI=10.1145/2579668 ACM DL
  • Licheng Chen, Zhipeng Wei, Zehan Cui, Mingyu Chen, Haiyang Pan, and Yungang Bao. CMD: classification-based memory deduplication through page access characteristics. In Proceedings of the 10th ACM SIGPLAN/SIGOPS international conference on Virtual execution environments (VEE '14), pp. 65-76. VEE2014_CMD.pdf

    2013

    • Zhongbin Zha, Zehan Cui, Yongbing Huang, Licheng Chen, Yungang Bao, Mingyu Chen. Memory Access Characteristics Analysis based on Clustering Sampling,  In National Annual Conference on High Performance Computing in China 2013 (HPC China 2013), Guilin, China, October 27-31, 2013 (in Chinese), pp. 279-286.EMAT_HPC_China_2013.pdf
    • Licheng Chen, Yanan Wang, Zehan Cui, Yongbing Huang, Yungang Bao, Mingyu Chen. Scattered Superpage: A Case for Bridging the Gap between Superpage and Page Coloring,  In Proceedings of The 31st IEEE International Conference on Computer Design (ICCD 2013), Asheville, NC, USA, October 6-9, 2013, pp. 177-184.ICCD2013_Scattered_Superpage_Proceeding.pdf
    • Licheng Chen, Yongbing Huang, Yungang Bao, Guangming Tan, Zehan Cui, Mingyu Chen. A Study of Leveraging Memory Level Parallelism for DRAM System on Multi-Core/Many-Core Architecture,  In Proceedings of The 11th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA-13), Melbourne, Australia, 16-18 July, 2013, pp. 1206-1215.ISPA2013_VCM_Proceeding.pdf
    • Licheng Chen, Zehan Cui, Yungang Bao, Mingyu Chen, Linfeng Shen, Qi Liang. An Approach for Monitoring Memory Address Traces with Functional Semantic Information,  Journal of Computer Research and Development, 50(5):1100-1109, 2013 (in Chinese).HMTT_FBI_JCRD.pdf

    2012

    • Zehan Cui, Licheng Chen, Mingyu Chen, Yungang Bao, Yongbing Huang, Huiwei Lv, Evaluation and Optimization of Breadth-First Search on NUMA Cluster,  Cluster Computing (CLUSTER), 2012 IEEE International Conference on , vol., no., pp.438,448, 24-28 Sept. 2012.CLUSTER12_BFS_Proceeding.pdf
    • Lei Liu, Zehan Cui, Mingjie Xing, Yungang Bao, Mingyu Chen, and Chengyong Wu. A software memory partition approach for eliminating bank-level interference in multicore systems,  In Proceedings of the 21st international conference on Parallel architectures and compilation techniques (PACT '12). ACM, New York, NY, USA, 367-376.PACT2012-Software-Bank-Partition.pdf
    • Yongbing Huang, Zehan Cui, Licheng Chen, Wenli Zhang, Yungang Bao, and Mingyu Chen. HaLock: hardware-assisted lock contention detection in multithreaded applications,  In Proceedings of the 21st international conference on Parallel architectures and compilation techniques (PACT '12). ACM, New York, NY, USA, 253-262.PACT2012-HaLock.pdf
    • Pengfei Zhu, Mingyu Chen, Yungang Bao, Licheng Chen, and Yongbing Huang. Trace-driven simulation of memory system scheduling in multithread application,  In Proceedings of the 2012 ACM SIGPLAN Workshop on Memory Systems Performance and Correctness (MSPC '12). ACM, New York, NY, USA, 30-37.MSPC12-MemorySimulation.pdf
    • Licheng Chen, Zehan Cui, Yungang Bao, Mingyu Chen, Yongbing Huang, Guangming Tan. A Lightweight Hybrid Hardware/Software Approach for Object-Relative Memory Profiling,  In Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems and Software(ISPASS'2012). IEEE Computer Society, Washington, DC, USA, 46-57.ISPASS2012_Object_Memory_Profiling.pdf

    2011 and Before

    • Zehan Cui; Yan Zhu; Yungang Bao; Mingyu Chen, A fine-grained component-level power measurement method,  Green Computing Conference and Workshops (IGCC), 2011 International , vol., no., pp.1,6, 25-28 July 2011.IGCC2011_Component_Power_Mesurement.pdf
    • Licheng Chen, Yongbing Huang, Yungang Bao, Onur Mutlu, Guangming Tan, Mingyu Chen, Poster: Revisiting Virtual Channel Memory for Performance and Fairness on Multi-Core Architecture,  Proceedings of the international conference on Supercomputing (ICS'11, poster paper)Poster_ICS11_VCM.pdf
    • Dan Tang, Yungang Bao, Weiwu Hu, Mingyu Chen, DMA Cache: Using On-Chip Storage to Architecturally Separate I/O Data from CPU Data for Improving I/O Performance, to appear in the 16th IEEE International Symposium on High-Performance Computer Architecture (HPCA-16), 2010. HPCA10-DMACache.pdf
    • Dan Tang, Yungang Bao, Yunji Chen, Weiwu Hu, Mingyu Chen, Exploiting the Produce-Consume Relationship in DMA to Improve I/O Performanc, Workshop on The Influence of I/O on Microprocessor Architecture (IOM-2009) in conjunction with the 15th International Symposium on High-Performance Computer Architecture (HPCA-15), Raleigh, North Carolina, February 15, 2009.IOM_DMA_Cache.pdfIOM_DMA_Cache.ppt
    • Yungang Bao, Mingyu Chen, Yuan Ruan, Li Liu, Jianping Fan, Qingbo Yuan, Bo Song, Jianwei Xu, "HMTT: A Platform Independent Full-System Memory Trace Monitoring System",  International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS'08),Annapolis, Maryland, USA, June 2-6, 2008.Remote_Memory.pdf
    • Li Liu, Mingyu Chen, Yungang Bao, Jianwei xu,Jianping Fan, A Network Memory Architecture Model and Performance Analysis, International Conference on Networking, Architecture, and Storage (NAS'08 poster), 2008.baoyg_VirtualChannel.pdf
    • Yungang Bao, Mingyu Chen,Jianping Fan, A Virtual Channel Mechanism for Memory Controller Design in the Multicore Era, Thirteenth Interna tional Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'08 poster),Seattle, WA, USA, March 1-5, 2008.

    Technical Reports:

    • Yungang Bao, Jinyong Zhang, Yan Zhu, Dan Tang, Yuan Ruan, Mingyu Chen, Jianping Fan, HMTT: A Hybrid Hardware/Software Tracing System for Bridging Memory Trace's Semantic Gap,  Report number: CAS-ICT-TECH-REPORT-20090327,   arXiv:1106.2568v1,   http://arxiv.org/abs/1106.2568 1106.2568v1.pdf
    • Yuan Ruan, Yungang Bao, Mingyu Chen, Jianping Fan, The design and implementation of MTT -- a hardware-based Memory Trace Tool, Technical_Report_070528 (in Chinese).