The tutorial slides are available for downloading at here: HPCA2013-Tutorial-HMTT.pdf.
We will give a tutorial on HMTT at HPCA 2013 in Shenzhen, China.
The memory system has been drawn enormous research efforts in the past decades due to its fundamental and critical impact on the performance of computer systems. The advent of mutlicore era is increasingly imposing new challenges such as scalability, power and quality of service (QoS). Researchers usually resort to trace-driven memory simulation for studying memory systems in which collecting a complete and detailed address trace is the fundamental step. Yet this step is tremendously time-consuming and difficult, especially for complex workloads involving multiple processes, OS and even I/O etc.
In this tutorial, we will present our efforts to address this challenge. The target audience of the tutorial is computer architecture researchers who are interested in memory system, performance profiling and so forth.
Researchers with some knowledge of computer architecture are welcome to participate in this tutorial.
In this tutorial, we will present our efforts to address this challenge. Specifically, we will introduce the following topics:
- Design and Implementation of HMTT. We will present the design and implementation of hardware/software Hybrid Memory Trace Tool (HMTT) which adopts a hardware snooping approach to collect physical addresses on memory buses and a software encoding approach to translate high-level information (e.g., page faults, function calls and DMA etc.) into specific memory addresses that can be captured by the hardware. By combining the advantages of both hardware and software, HMTT is able to collect complete and detailed memory traces with high-level information for complex real world applications running on real systems.
- HMTT-based Tools. We will also demonstrate two HMTT-derivative tools, such as object-relative memory profiling, low-overhead lock profiling and power profiling, to exemplify the strength of HMTT.
- Usage of HMTT. We will illustrate how HMTT assists page-coloring approach to eliminate DRAM bank-level interference on real machines and how HMTT is used for studying I/O memory access behavior.
- Prototype demonstration. We will bring a prototype to demonstrate how to use HMTT.
Special Gifts (New Event)
We offer free memory traces to first ten attendees. The traces are collected on real machines, with abundant important information, such as timestamp, pid, cpu-request/io-request, r/w, virt_addr and phys_addr. However, the trace sizes are quite large, being dozens of Gigabytes.
We also suggest those who are interested in the traces bring a disk to the tutorial.
The tutorial will take place on Sunday afternoon, February 24th.
14:00~14:20 Lecture 1: Principle, design and implementation of HMTT
14:20~14:30 Lecture 2: Trace format
14:30~14:40 Demo 1: Converting physical address trace to virtual address
14:40~15:05 Lecture 3: Using HMTT for I/O DMA research
15:05~15:30 Lecture 4: Using HMTT for lock profiling and function-level monitoring
16:00~16:10 Demo 2: Object-level profiling
16:10~16:20 Demo 3: FPGA supported address filter
16:20~16:30 Demo 4: Virtual machine profiling
16:30~16:45 Lecture 5: Roadmap and future work
18:00~20:00 Main Conference Welcome Reception